FPGA Manager PCIe

Enclustra’s FPGA Manager PCIe solution is optimized for Intel (Altera) and Xilinx FPGAs and allows for easy and efficient data transfer between a host and a FPGA over a PCI Express interface.

The solution includes a host software library (DLL/SO), a PCI Express driver, and a suitable IP core for the FPGA. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Streaming and memory-mapped accesses are supported.

• Over 1500 MBytes/sec data
  transfer rate per direction
• Low latency
• Runs on Windows and Linux¹
• Supports C, C++, C#/.NET and MATLAB® user applications
• Up to 4 GByte data transfer in a single DMA transfer
• Infinite-length streaming transfers
• Up to 128K DMA descriptors pre-fetching
• Supports packet-based or stream-based data transfers
• Configurable user datapath width (64-bit / 128-bit / 256-bit)
• Supports TLP completion reordering
• Power management capabilities
  on Windows (sleep/power-off and resume)

• Complete and easy to use solution for communication between FPGA and host
• No need for dealing with complexity of underlying protocols
• Runs straightforward on Windows and Linux
• Universal and friendly user space API on Windows and Linux¹
• Evaluation kits and reference design available

• Streaming data transfer between FPGA and host
• Memory-mapped access to FPGA AXI bus
• Up to 32 independent DMA channels (up to 16 in each direction)
• Standard AXI Stream interface for user integration
• Flexible and configurable
• PCIe Gen 1, Gen 2 and Gen 3
• ×1, ×2, ×4, ×8 lanes
• Easy firmware Flash update capability

• FPGA Manager PCIe IP Core
  • VHDL source files (plain or encrypted, depending on product options)
  • Reference design
  • User manual
• FPGA Manager PCIe DLL/SO
  • Binary DLL/SO
  • API header files
  • API user manual
• FPGA Manager PCIe driver
  • Binary File
• FPGA Manager PCIe Reference Design
  • Reference design top-level VHDL file (plain VHDL)
  • UCF / XDC / SDC constraint files (depending on product options)
  • Xilinx® ISE / Xilinx Vivado™ / Intel® Quartus® project files (depending on product options)
  • Top-level simulation test bench file (plain VHDL)
  • Top-level simulation ModelSim project file
  • Documentation

• The license is granted to an “authorized site”, meaning a single geographical location with radius < 5 km in which the licensee conducts business.
• The licensed material can be used for unlimited projects and/or end products developed at the authorized site.

• Test & Measurement
• Image Processing
• Smart Cameras
• Software Defined Radio

• Enclustra Mars Family FPGA Modules
• Enclustra Mars Family Base Boards
• Enclustra Mercury Family FPGA Modules
• Enclustra Mercury Family Base Boards